Wu Zhenhua

Zhenhua Wu, Professor, Ph.D. Supervisor at Zhejiang University. Research interests: computational nanoelectronics and its applications, including carrier transport in nanoscale transistors and Machine Learning + TCAD simulation methods. He has published over 80 papers as first or corresponding author in leading international journals (IEEE EDL/TED, PRL/PRB/PRApplied, APL/JAP), including 2 ESI highly cited papers. He has also published 30+ conference papers, including 8 papers at IEDM and 2 papers at the VLSI Technology Symposium. He holds over 30 Chinese invention patents and 4 U.S. patents. His publications have been cited more than 4,000 times, with an H-index of 31. He was listed in Elsevier's “Global Top 2% Scientists” (2024). Several of his research results have been cited and followed by leading research institutions and companies, and he has established strong academia–industry collaborations.

Education Background

2002.09 – 2006.06, Nanjing University, B.Sc. in Physics

2006.09 – 2011.07, Institute of Semiconductors, Chinese Academy of Sciences, Ph.D. in Condensed Matter Physics

 Work Experience

2024.04 – Present, Zhejiang University, Center for Quantum States and Devices, Professor, Ph.D. Supervisor

2016.06 – 2024.03, Institute of Microelectronics, Chinese Academy of Sciences, Researcher, Ph.D. Supervisor

2013.03 – 2016.05, Samsung Electronics Semiconductor R&D Center, Senior R&D Engineer

2011.09 – 2013.02, Samsung Electronics Semiconductor R&D Center, R&D Engineer

Honors and Awards

2019, Excellent Undergraduate Supervisor, University of Chinese Academy of Sciences

2018, CAS Overseas Talent Program

Research grant

1.National Natural Science Foundation of China (Key Project), “Customizable Common-Mode Baseband Theory and Technology for 5G/6G Full-Scenario Applications”, 2024/01 – 2028/12, Sub-project 3 Leader

2.National Key R&D Program of China, “Wafer-Level ‘All-in-One’ Nano-Device and Chip Integration”, 2021/12 – 2026/11, Sub-project 2 Leader

3.National Natural Science Foundation of China (General Project), “2D Ferroelectric Heterojunction Devices”, 2022/01 – 2025/12, Principal Investigator

4.National Natural Science Foundation of China (Key Project), “NC-FinFETs with Ultrathin ZrO2 Gate Dielectrics and Reliability Study”, 2020/01 – 2023/12, Sub-project 2 Leader

5.National Natural Science Foundation of China (General Project), “High-Mobility 2D Indium Selenide and Its Heterostructures: Physical Properties, Quantum Transport, and Device Applications”, 2018/01 – 2021/12, Principal Investigator

Publications and patents in the past five years

Direction 1: Physics of Nanoscale Devices

1. Xu, H.; Yao, J.; Yang, Z.; Cao, L.; Zhang, Q.; Li, Y.*; Du, A.; Yin, H.; Wu, Zhenhua*, Physical Insights of Si-Core-SiGe-Shell Gate-All-Around Nanosheet pFET for 3 nm Technology Node, IEEE Transactions on Electron Devices, 2023, 70: 3365.[Corresponding Author]

ua*, A Three-Dimensional Simulation Study of the Novel Comb-Like-Channel Field-Effect Transistors for the 5-nm Technology Node and Beyond, IEEE Transactions on Electron Devices, 2022, 69: 4786. [Corresponding Author]

3. Gan, W.; Luo, K.; Qi, G.; Prentki, R.; Liu, F.; Huo, J.; Huang, W.; Bu, J.; Zhang, Q.; Yin, H.; Guo, H. Lu, Y.; Wu, Zhenhua*, A Multiscale Simulation Framework for Steep-Slope Si Nanowire Cold Source FET, IEEE Transactions on Electron Devices, 2021, 68: 5455. [Corresponding Author]

4. Huang, S.^#; Wu, Zhenhua^#; Xu, H.; Guo, J.; Xu, L.; Duan, X.; Chen, Q.; Yang, G.; Zhang, Q.; Yin, H.; Wang, L.*; Li, L.*; Liu, Ming, Geometric Variability Aware Quantum Potential based Quasi-ballistic Compact Model for Stacked 6nm-Thick Silicon Nanosheet GAA-FETs, 2021, International Electron Devices Meeting (IEDM). [Co-First Author]

5.Zhan, G.; Zhu, T.; Yao, J.; Luo, K.; Yin, H.; Zhang, S. and Wu Zhenhua*, Quantum transport for the gate-length scaling limit of Si nanowire field-effect transistors based on calibrated k · p Hamiltonian parameters. Phy. Rev. Appl., 2025, 23: 034049.[Corresponding Author]

Direction 2: Post-Moore Novel Materials and Devices (Path-Finding)

1. Zhan, G.; Yang, Z.; Luo, K.; Zhang, S.; Wu, Zhenhua*, Large Magnetoresistance and Perfect Spin-Injection Efficiency in Two-Dimensional Strained -Based Room-Temperature Magnetic-Tunnel-Junction Devices, Physical Review Applied, 2023, 19: 014020. [Corresponding Author]

2. Xu, Y.; Zhang, C.; Li, W.; Li, R.; Liu, J.*; Liu, Z.; Wu Zhenhua*, High sensitivity ultraviolet graphene-metamaterial integrated electro-optic modulator enhanced by superlubricity, Nanophotonics, 2022, 11:3547.[Corresponding Author]

3. Shen S.; Wu, L.; Yang, S.; Yang, Q.; Liu, J.*; Wu, Zhenhua*, Optical energy harvesting in vibrate maglev graphite, Carbon, 2022, 187: 266. [Corresponding Author]

4. Zhou, M.; Zhou, C.; Luo, K.; Li, W.; Liu, J.*; Liu, Z.; Wu, Zhenhua*, Ultrawide bandwidth and sensitive electro-optic modulator based on a graphene nanoelectromechanical system with superlubricity, Carbon, 2021, 176: 228. [Corresponding Author]

5. Xia, Y.; Guo, S.; Xu, L.; Guo, T.; Wu, Zhenhua*; Zhang, S.*; Sensing Performance of SO2, SO3 and NO2 Gas Molecules on 2D Pentagonal PdSe2: A First-principle Study, IEEE Electron Device Letters, 2021, 42: 573. [Corresponding Author]

Direction 3: Advanced TCAD Simulation and DTCO Methodology

1. Luo, Y.; Zhang, Q.; Cao, L.; Gan, W.; Xu, H.; Cao, Y.; Gu, J.; Xu, R.; Yan, G.; Huo, J.; Wu, Zhenhua*, Yin, H.*, Investigation of Novel Hybrid Channel Complementary FET Scaling Beyond 3-nm Node from Device to Circuit, IEEE Transactions on Electron Devices, 2022, 69: 3581. [Corresponding Author]

2. Xu, H.; Gan, W.; Cao, L.; Yang, C.; Wu, J.; Zhou, M.; Qu, H., Zhang, S.*; Yin, H.; Wu, Zhenhua*, A Machine Learning Approach for Optimization of Channel Geometry and Source/Drain Doping Profile of Stacked Nanosheet Transistors, IEEE Transactions on Electron Devices, 2022, 69: 3568.[Corresponding Author]

3. Yang, Q.; Qi, G.; Gan, W.; Wu, Zhenhua*, Yin, H.; Chen, T.; Hu, G.; Wan, J.; Yu, S.; Lu, Y.*, Transistor Compact Model Based on Multigradient Neural Network and Its Application in SPICE Circuit Simulations for Gate-All-Around Si Cold Source FETs, IEEE Transactions on Electron Devices, 2021, 68: 4181.[Corresponding Author]

4.Gan, W.; Prentki, R.; Liu, F.; Bu, J.; Luo, K.; Zhang, Q.; Zhu, H.; Wang, W.; Ye, T.; Yin, H.; Wu, Zhenhua*; Guo Hong*, Design and Simulation of Steep-Slope Silicon Cold Source FETs With Effective Carrier Distribution Model, IEEE Transactions on Electron Devices, 2020, 67: 2243. [Corresponding Author]

5.Zhao. Y.; Wang, L.; Wu, Zhenhua, Schanovsky, F.; Xu, X.; Yang, H.; Yu, H.; Lai, J.; Liu, D.; Chuai, X.; Su, Y.; Wang, X.; Li, L.*; Liu, Ming*, A Unified Physical BTI Compact Model in Variability-Aware DTCO Flow: Device Characterization and Circuit Evaluation on Reliability of Scaling Technology Nodes, 2021, Symposium on VLSI Technology (VLSI). [Third Author]